In this paper, a data processing algorithm is proposed for controlling a system of stepper motors with the ability to move with acceleration in computer numerical control (CNC) machines. Based on the analysis of various approaches to accelerating the stepper motors movement, an algorithm was developed. The algorithm allows synchronized control of the stepper motor system, which ensures the same movement time for each motor within a valid range. A mathematical model of the control algorithm was developed and its hardware and software implementation on the FPGA based on the system-on-chip principle was presented. This implementation made it possible to control the system of stepper motors so that each unit is controlled in parallel and independently, and at the same time, the synchronism and accuracy of their movements within the valid range is ensured. The results of testing the algorithm on a 3D-printer present that the given algorithm provides the necessary accuracy and can be used in control systems for CNC machines and 3D-printers in particular.
Object detection is one of the most active research and application areas of neural networks. In this article we combine FPGA and neural networks technologies to solve the real-time object recognition problem. The article discusses the integration of the YOLOv3 neural network on the DE10-Nano FPGA. Slightly worse indicators of the main metrics (mAP, FPS, inference time) when operating a neural network on a De10-Nano board in comparison with more expensive solutions based on GPUs, are offset by differences in the cost and dimensions of the FPGA board used. Based on the results of the study of various methods for converting neural networks to FPGA, it was concluded that this architecture is applicable for solving problems of detecting objects on a video stream in real time.
This article analyzes new promising topological solutions for the on-chip communication subsystem for network-on-chip (NoCs). A study of Paley graphs as a subclass of circulant graphs is given. The main parameters (diameter, average path length, graph density, number of edges and degrees of vertices) of modifications of Paley graphs are studied using the direct product of Paley graphs with Paley graphs and ring graph. Other types of products of graphs are considered, namely strong, tensor and lexicographic. Due to the more preferable characteristics, the direct product of the graphs was chosen as the most suitable among the considered ones. A comparative analysis of obtained graphs is provided.
This paper provides an overview of existing network-on-a-chip (NoC) topologies. The study of Paley graphs as a topological graph basis for the design of NoC is carried out. Various modifications of circulant graphsare considered.The main focus of the research is directed to the study of the direct and root products of Paley graphs,the substantiation of the irrelevance of considering tensor, lexicographic and strong products of graphs is given. The comparison of the most important parameters of the graphs, which directly affect the main parameters of networks-on-chip, including the network bandwidth and the speed of data transfer between network nodes, is performed.
For analytically defined families of three-dimensional circulant networks with a parametric description, an analytical algorithm for finding shortest paths which has a common scheme for all networks of the family based on a given generating function was developed. A comparative analysis of three routing algorithms (analytical Two-terminal routing algorithm, Coefficients search on graph generators, and Dijkstra’s algorithm) for a variety of circulant networks from an analytically defined family was carried out. Estimates of the effectiveness of the considered routing algorithms for use in networks-on-chip were obtained.
Automatic classification of sound commands is becoming increasingly important, especially for embedded and mobile devices. Many of these devices contain both microphones and cameras. The manufacturers that develop and produce them would like to use the same methodology for sound and image classification tasks. It’s possible to achieve by representing sound commands as images, and then use convolutional neural networks when classifying images as well as sounds. In this research, we tried several approaches to the problem of sound classification that we applied in TensorFlow Speech Recognition Challenge organized by Google Brain team on the Kaggle platform. Here we show different representations of sounds (Wave frames, Spectrograms, Mel-Spectrograms, MFCCs) and apply several 1D and 2D convolutional neural networks to get the best performance. As a novelty of our work, we developed and trained from scratch two 1d network architectures that are topologically similar to 2d VGG and ResNet network types. These networks show similar performance with 2d networks when sound signal is represented by using melgrams. Our experiments reveal that we found appropriate sound representation and corresponding convolutional neural networks. As a result, we achieved good classification accuracy (91.8%) that allowed us to finish the challenge on 8-th place among 1315 teams.
This work is devoted to the study of application of new topologies in the design of networks‑on‑chip (NoCs). It is proposed to use two‑dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.
For a family of optimal two-dimensional circulant networks with an analytical description, two new improved versions of the shortest path search algorithm with a constant complexity estimate are obtained. A simple, based on the geometric model of circulant graphs, proof of the formulas used for the shortest path search algorithm is given. Pair exchange algorithms are presented, and their estimates are given for networks-on-chip (NoCs) with a topology in the form of the considered graphs. New versions of the algorithm improve the previously proposed shortest path search algorithm for optimal generalized Petersen graphs with an analytical description. The new proposed algorithm is a promising solution for the use in NoCs which was confirmed by an experimental study while synthesizing NoC communication subsystems and comparing the consumed hardware resources with those when other previously developed routing algorithms.
This paper presents a brief description of a method of automated parametric and structural optimization of temperature control systems of electronic equipment using criteria of solution effectiveness evaluation. Methods and models, that allow automating the process of choosing both thermal regulation (temperature control) tools for electronic equipment and their parameters, are proposed. The problems of formalization of temperature control means selection criteria for electronic components through the cost coefficients, specified by the expert, are considered. The criteria for optimal design allow estimating the effectiveness of heat balance diagram and temperature control means, as well as their parameters. The optimization algorithm, proposed in the article, considers a variety of different continuous states of variable heat balance diagram that depends on the thermal model temperature control means and their parameters. At the same time, temperature control means, that have the greatest impact on the thermal model at the next step with taking into account the cost function, are selected. As an example, the optimal synthesis of temperature control means of a typical electronic equipment block with taking into account the necessity to assess the feasibility of using aluminum heat sinks with electronic components as compared to heat pipes was made.
This work includes a review of MIPS architecture processor cores and a review of network topology consisting of routers. It was demonstrated by realization of 2 multiprocessor systems developed on the basis of mesh topology using modified schoolMIPS soft-processor cores, in which architecture additional blocks and instructions were added, and routers with XY routing. As a result, the obtained NoC performance is up to 1.87 Gbit/s (4 processor cores), and up to 1.54 Gbit/s (10 processor cores). The extended processor core schoolMIPS consumes 452 ALMs and 1692 bits of memory; NoC of 4 processor cores takes 2223 ALMs and 9136 bits of memory; NoC of 10 processor cores – 5696 ALMs and 22840 bits of memory. The obtained results suggest that there is a possibility of NoC development with the number of nodes up to 200 nodes on Stratix IV GX EP4SGX230 (DE4).
In this paper, a review of various high-level models of networks-on-chip, their performance capabilities, and characteristics was carried out. As a result, the BookSim simulator was chosen. Application of circulant topologies for implementation of communication subsystems in networks-on-chip (NoCs) as alternatives to other regular topology was proved. The process of modifying the BookSim simulator described allowed high-level modeling of NoCs with any topologies (including two‑dimensional circulants), as well as testing new routing algorithms in such networks.
The paper presents the implementation of a dynamic routing algorithm intended for use in networks-on-chip with a circulant topology with three generatrices of type C(N; s1, s2, s3) for finding the shortest routes between any two network nodes. The algorithm can be implemented as a RTL state machine in routers for NoCs. The proposed algorithm was tested on sets of optimal circulants. Compared with the classical algorithms A* or Dijkstra, the proposed algorithm does not require to calculate the entire path of the packet, but calculates the port number to which the packet should be sent so that it can reach the destination node. This makes it possible to significantly simplify the structure of the NoC router.
The development of multi-core processor systems is a demanded branch of science and technology. The appearance of processors with dozens and hundreds of cores poses to the developers the question of choosing the optimal topology capable to provide efficient routing in a network with a large number of nodes. In this paper, we consider the possibility of using multiplicative circulants as a topology for networks-on-chip. A specialized routing algorithm for networks with multiplicative circulant topology, taking into account topology features and having a high scalability, has been developed.
The article presents Java and HDL-models, which are the basis of the new hybrid NoC model. Based on it, modeling of mesh, torus topologies and two-dimensional circulant for NoC was carried out.